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finte k feature integration technology inc. apr/2004 v0.36 F72603R F72603R fintek acpi controller ic datasheet release date: apr 2004 revision: version 0.36
finte k feature integration technology inc. apr 2004 v0.36 F72603R F72603R datasheet revision history version date page revision history 0.1 jan.2003 original version 0.2 feb.2003 revise register description 0.33 aprl.2003 revise vendor id and i2c addr can be programmable 0.34 july.2003 revise some description 0.36 apr 2004 revise (1) register index 01 initial value :from 1f to 03 (2) version id index5c : from 10 to 12 please note that all data and specifications are subject to change without notice. all t he trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support applia nces, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
finte k feature integration technology inc. apr 2004 v0.36 F72603R table of contents 1. general de scription ............................................................................................................ ...............................1 2. features....................................................................................................................... ......................................1 3. key specifications ............................................................................................................. ................................1 4. pin config uration .............................................................................................................. .................................2 5. block diagram .................................................................................................................. .................................3 6. pin descr iptions............................................................................................................... ..................................3 6.1 power pins ............................................................................................................................. 4 6.2 reset & power good signal pins ............................................................................................. 4 6.3 linear & switch controller ..................................................................................................... 4 6.4 charge pump ..................................................................................................................... 5 6.5 power led ........................................................................................................................ 5 6.6 control signal and others ..................................................................................................... 5 7. functional de scription ......................................................................................................... ..............................6 7.1 acpi state ............................................................................................................................ 6 7.2 charge pump ........................................................................................................................ 6 7.3 soft-start .............................................................................................................................. 7 7.5 reference voltage .................................................................................................................. 7 7.6 access interface .................................................................................................................... 7 8. registers de scription.......................................................................................................... ...............................9 8.1 pcirst_n delay function register, default 0x03h ? index 01h ....................................................... 9 8.2 pwokout delay function register, default 0x07h ? index 02h ...................................................... 9 8.3 pled register, default 0x00h ? index 03h ................................................................................ 10 8.4 dualgat, usbgat, lr_drv mode select register, default 0x10h ? index 04h .............................. 11 8.5 over-voltage configuration register for vref and lr regulator default 0x00h ? index 05h ................ 11 8.6 manufacturer id high byte, default 0x03h, read only ? index 5ah ............................................... 12 8.7 manufacturer id low byte, default 0x02h, read only ? index 5bh ................................................ 12 8.8 chip id, default 0x10h, read only ? index 5ch ........................................................................ 12 8.9 revision id, default 0x19h, read only ? index 5dh .................................................................... 12 8.10 revision id, default 0x34h, read only ? index 5eh ................................................................. 12 8.11 vender id, default 0xa0h, read only ? index 6ah .................................................................. 12 8.12 vender id, default 0xa0h, read only ? index 6bh .................................................................. 12 8.13 register f0 (test mode, default 0x00h) .................................................................................. 12 8.14 register f1 (test mode, default 0x00h) .................................................................................. 13 8.13 register ff (i2c addr program defaultt 0x5eh) ..................................................................... 13 9. electrical ch aracteristic ...................................................................................................... ..............................14
finte k feature integration technology inc. apr 2004 v0.36 F72603R 9.1 absolute maximum ratings ...................................................................................................... 14 9.2 dc characteristics ................................................................................................................. 14 9.3 ac characteristics .................................................................................................................. 16 10. package specif ication .......................................................................................................... ............................17 11 application circuit ......................................................................................................... ..............................................1
finte k feature integration technology inc. -1 - apr 2004 v0.36 F72603R 1. general description the F72603R is a fully compliant acpi controller ic. us ed with an atx power supply, this chip integrates one linear controller, four switch controller, monitoring and power signal control function into 28 pin ssop package. the F72603R not only provides one adjustable linear regulator and four switch controllers but also integrates a charge pump engine to provide higher driving voltage for appropriate gate during standby. it also integrates power ok and reset signal circuit. on t he other hand, this chip of fers current limiting that protect each output, and provides soft-start function fo r linear regulator to avoid rush current. the power led and suspend led are prog rammable and compliant with pc2001. this chip is in vsb 5v operation and 28pin ssop package. 2. features ? support 1 adjustable linear regulator ? provide 4 switch signal for power control ? 2 pwrok input signals(typically from atx_pw gd & hwrstin) and 1 pwrok output signal ? resume reset signal output ? 1 input reset signal to 3 output reset signals buffer ? programmable power dual led compliant with pc2001 ? power up soft-start(ss) for linear regulator ? provide adjustable 1.25v reference voltage(v ref ) ? provide vsb 9v voltage(charge pump) fo r generating different kind of voltage ? 2-wire serial interface ? 28 pin ssop package & vsb 5v operation 3. key specifications ? supply voltage 4.5v to 5.5v
finte k feature integration technology inc. -2 - apr 2004 v0.36 F72603R 4. pin configuration pcirstin# cp vsb c1 dualgate slotrst# c2 usbgate vccgate vref devicerst# gnd scl pwokin1 sda hddrst# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 22 25 26 27 24 23 28 17 18 19 16 15 20 pwokin2 pwokout ps_on# pled sled strgate lr_drv ss gnd s5in# rsmrst# lr_sen F72603R
finte k feature integration technology inc. -3 - apr 2004 v0.36 F72603R 5. block diagram led reset circuit pwok circuit control circuit charge pump control register vref vsb slotrst# devicerst# hddrst# pcirstin# pwokin1 pwokin2 pwokout sda scl gnd sled pled ps_on# vref ss gnd s5in# lr_drv lr_sen c1 dualgat e c2 cp vccgate usbgate strgate rsmrst# i2c interface linear regulator osc control circuit control circuit 6. pin descriptions i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability i/o 12ts - ttl level and schmitt trigger o 12 - output pin with 12 ma source-sink capability o 24v4 - output pin with 24 ma source-sink capability, output 4v aout - output pin(analog) od 12 - open-drain output pin with 12 ma sink capability in t - ttl level input pin in ts - ttl level input pin and schmitt trigger ain - input pin(analog)
finte k feature integration technology inc. -4 - apr 2004 v0.36 F72603R 6.1 power pins pin no pin name type description 1 vsb 11 gnd 19 gnd pwr power pins 6.2 reset & power good signal pins pin no pin name type pwr description 2 slotrst# o 24v4 vsb5v slot_rst # is an active low signal and act as ?1 to 3? buffer output. 3 devicerst# od 24 vsb5v devicerst# is an active low signal and acts as ?1 to 3? buffer output . open drain output. 4 hddrst# od 24 vsb5v hddrst# is an active low signal and acts as ?1 to 3? buffer output . 5 pcirstin# in ts vsb5v pcirst# is an active low signal and acts as ?1 to 3? buffer input . 6 pwokin1 in ts vsb5v power good schmitt trigger input 7 pwokin2 in ts vsb5v power good schmitt trigger input 8 pwokout od 16 vsb5v power good schmitt trigger output 16 rsmrst# od 12 vsb5v rsmrst# output is an active low signal(delay 66ms) 6.3 linear & switch controller pin no pin name type pwr description 21 strgate aout vsb9v connect this pin to the gate of a suitable n-channel mosfet 22 usbgate aout vsb9v connect this pin to the gate of a suitable n-channel mosfet 23 vccgate aout vsb9v connect this pin to the gate of a suitable n-channel mosfet 24 dualgate aout vsb9v connect this pin to the gate of a suitable n-channel mosfet 18 lr_sen ain vsb5v sense the voltage of linear regulator 20 lr_drv aout vsb9v connect this pin to the gate of a suitable n-channel mosfet
finte k feature integration technology inc. -5 - apr 2004 v0.36 F72603R 6.4 charge pump pin no pin name type pwr description 25 chrpmp p vsb9v charge pump output (9v nominal). decouple this pin with 1uf ceramic capacitor 26 c2 ain vsb9v positive end of charge pump capacitor 27 c1 aout vsb9v negative end of charge pump ca pacitor. connect a 1uf ceramic capacitor between pin27 (-) and pin26(+) 6.5 power led pin no pin name type pwr description 12 sled od 24 vsb5v suspend led. can be programmed by setting register 13 pled od 24 vsb5v power led. can be programmed by setting register 6.6 control signal and others pin no pin name type pwr description 9 sda i/od 12 vsb5v 2-wire serial bus data. leakage free. 10 scl in ts vsb5v 2-wire serial bus clock. leakage free. 14 ps_on# in ts vsb5v schmitt trigger input. connect to at x power. while connecting an inverter between this pin and atx power, this pin will act as s3# input. 15 s5in# in ts vsb5v acpi control signal governing the soft off state s5(low active) 17 ss ain vsb5v soft-start. connect this pin to a small ceramic capacitor to determine the soft-start rate. the value of capacitor is bigger, the slew rate is slower. 28 vref aout vsb5v provide 1.25v reference voltage. as for vref over-voltage, please refer to register description (index 05h)
finte k feature integration technology inc. -6 - apr 2004 v0.36 F72603R 7. functional description 7.1 acpi state the advanced configuration and power interface (acpi) is a system for controlling the use of power in a computer. it lets computer manufacturer and user to determine the computer?s power usage dynamically. there are three acpi states that are of primary concer n to the system designer and they are designated s0, s3 and s5. s0 is a full-power state and in this state, the co mputer is being actively used. the other two are called sleep states and reflect different power consumption when power-down. s3 is a state the processor is powered down but the last state is being stored in memory which is still active. s5 is a state that memory is off and the last state of the processor has been stored to the hard disk. ta ke s3 and s5 as comparison, since memory is fast, the computer can quickly come back to full-power state. but the disk is slower than the memory, the computer takes longer time to come back to full-power state. ho wever, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen: s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s5 s3 is illegal transition and won?t be allowed by st ate machine. in order to get to s5 from s3, it is necessary to enter s0 first. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. 7.2 charge pump the F72603R incorporated with an embedded charge pump to provide higher driving voltage. pin 22(cp) supports 10ma driving curr ent and ensures 9v output voltage or above. in main operation, the vsb9v signals of F72603R are run from the +12v supplied by atx power which also supplies to other mosfet gates. however, during standby state, the +12v will be off and it needs to provide power to the chip and the appropriate gates. therefore F72603R incorporated with a free running charge pump. as shown in schematic, there is a capacitor connected between pin 23 and 24 of the F72603R acts as a charge pump with internal diodes. the 12v input must has a serial diode to prevent back-feeding the c harge pump to the +12v main when in standby. it also needs a bypass capacitor connected with 12v i nput line to filter high-frequency noise.
finte k feature integration technology inc. -7 - apr 2004 v0.36 F72603R 7.3 soft-start pin27 of the F72603R acts as a soft-start. as shown in schematic, a ceramic capacitor is attached between this pin and ground. when power is first applied to the chip, a c onstant current is applied from the pin into an external capacitor, linearly ramping up the voltage. this ramp in tu rn controls the internal reference of F72603R providing a soft-start for linear regulator. as for switches, they must be either on or off in the system therefore soft-start has no effect on them . it is important to know soft-start is not an enable signal; pulling it low will not be sure to turn off all outputs. but if there are appropriate signals asserted, the switches will be tu rn on at once. the actual state of F72603R on power up will be determined by the controlled i nput signal. and the soft-start is effective only during power on. during a transition between states (not during pow er on), such as s3 to s0, the linear regulators won?t be asserted. 7.5 reference voltage the pin28 (vref) is an output pin that is driven by a small output buffer to provide the 1.25v reference voltage to other devices in the system. 7.6 access interface the F72603R can be connected to a compatible 2-wire serial system management bus as a slave device under the control of the master device, using two device te rminals scl and sda. the F72603R can provide a clock signal to the device scl pin and read/write data from/to the device through the device sda pin. the operation of device to the bus is described with details in the following sections. (a) smbus write to internal address register followed by the data byte 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by 603r r/w ack by 603r scl sda d7 d6 d5 d4 d3 d2 d1 d0 stop by master scl sda (continued) 780 78 0 78 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 1. serial bus write to internal address register followed by the data byte
finte k feature integration technology inc. -8 - apr 2004 v0.36 F72603R (b) serial bus write to internal address register only 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by 603r r/w ack by 603r scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte figure 2. serial bus write to internal address register only stop by master (c) serial bus read from a register with the internal address register prefer to desired location 0 start by master 01011 01 d7 d6 d5 d4 d3 d2 d1 d0 ack by master r/w ack by 603r scl sda 780 78 0 frame 2 internal index register byte frame 1 serial bus address byte figure 3. serial bus read from internal address register stop by master
finte k feature integration technology inc. -9 - apr 2004 v0.36 F72603R 8. registers description 8.1 pcirst_n delay function register, default 0x 03 h ? index 01h bit name pwd description 7 slot_softrst 0 slotrst_n software reset, when set to 1, it will produce one low pulse signal to slotrst_n, and the pulse width is set by register0 [1:0] (after reset, the bit will clean to 0) 6 dev_softrst 0 devicerst_n software reset, when set to 1, it will produce one low pulse signal to devicerst_n, and the pulse width is set by register0 [1:0] (after reset, the bit will clean to 0) 5 hdd_softrst 0 hddrst_n software reset, when se t to 1, it will produce one low pulse signal to hddrst_n, and the pulse width is set by register0 [1:0] (after reset, the bit will clean to 0) 4 slot_delay_en 0 enable the delay function of slotrst_n from pcirst_n, default = 0, if set to 1, the delay function is enable, the delay time is set by register0 [1:0] 3 dev_delay_en 0 enable the delay function of devicerst_n from pcirst_n, default = 0, if set to 1, the delay function is enable, the delay time is set by register0 [1:0] 2 hdd_delay_en 0 enable the delay function of hddrst_n from pcirst_n, default = 0, if set to 1, the delay function is enable, the delay time is set by register0 [1:0] 1 delay[1] 1 0 delay[0] 1 the slotrst_n and devicers t_n and hddrst_n signals are delayed from pcirst_n by followed setting 00 1ms 01 2ms 10 3ms 11 4ms 8.2 pwokout delay function register, default 0x07h ? index 02h bit name pwd description
finte k feature integration technology inc. -10 - apr 2004 v0.36 F72603R 7 pwok_softrst 0 pwokout software reset, set to 1, it will produce one low pulse signal to pwokout, and the pulse width is set by register 01 [1:0] (after reset, the bit will clean to 0) 6 reserved 0 reserved 5 reserved 0 reserved 4 reserved 0 reserved 3 reserved 0 reserved 2 pwok_delay_en 1 enable the delay function of pwokout from pwokin(*1), default = 0, if set to 1, the delay function is enable, the delay time is set by register1 [1:0] 1 delay[1] 1 0 delay[0] 1 the pwokout signals are delayed from pwokin(*1) by followed setting 00 100ms 01 200ms 10 300ms 11 400ms *1 pwokin = pwokin1 & pwokin2 8.3 pled register, default 0x00h ? index 03h bit name pwd description 7 prog_en 0 set to 1 to enable program pled an d sled frequency, set to 0 to hardware setting 6 pled_freq[2] 0 5 pled_freq[1] 0 4 pled_freq[0] 0 111 : led pin is tri-state (od pin) or drived high (o pin) 110 : led pin is 1 hz toggle pulse with 50 duty cycle 101 : led pin is 1/2 hz toggle pulse with 50 duty cycle 100 : led pin is 1/4 hz toggle pulse with 50 duty cycle 000 : led pin is drived low 3 led_mode 0 pled_mode select 2 sled_freq[2] 0 1 sled_freq[1] 0 sled_freq[0] 0 111 : led pin is tri-state (od pin) or drived high (o pin) 110 : led pin is 1 hz toggle pulse with 50 duty cycle 101 : led pin is 1/2 hz toggle pulse with 50 duty cycle 100 : led pin is 1/4 hz toggle pulse with 50 duty cycle 000 : led pin is drived low
finte k feature integration technology inc. -11 - apr 2004 v0.36 F72603R 8.4 dualgat, usbgat, lr_drv mode select register, default 0x12h ? index 04h bit name pwd description 7 dual_mode[1] 0 6 dual_mode[0] 0 dualgat mode control, default mode is dual mode, 00: dual mode, 01: str mode, 10: power off, 11: reserved 5 usb_mode[1] 0 4 usb_mode[0] 1 usbgat mode control, default mode is str mode, 00: dual mode, 01: str mode, 10: power off, 11: reserved 3 lr_mode[1] 0 2 lr_mode[0] 0 linear regulator mode control, default mode is dual mode, 00: dual mode, 01: str mode, 10: power off, 11: reserved 1 mode 1 mode=0, linear regulator is used 1 mos, mode=1, is used 2 mos 0 reserved 0 * the dualgat and usbgat and lr must switch with vccgat 8.5 over-voltage configuration register for vref and lr regulator default 0x08h ? index 05h bit name pwd description 7 en_vref 0 set to 1 enable to increase vref, the increase percentage is set by bit[6:5]; set to 0 will not increa se the percentage of vref 6 ov_vref[1] 0 5 ov_vref[0] 0 vref over voltage percentage 00 1% 01 2% 10 3% 11 4% 4 uv_en 0 set to 1 to enable under voltage protect, when the lr_sen is below 1.0v, the under voltage event occurs, if uv_en is set to 1, it will sd the linear regulator. 3 vsb_pwr_loss 1 when vsb 5v comes, it will set to 1, and write 1 to clear it 2 uv_sel 0 uv_sel : 0 the under-voltage protect time is from pwok is high uv_sel : 1 the under-voltage protect time is from ss_ok 1 reserved 0 reserved 0 reserved 0 reserved
finte k feature integration technology inc. -12 - apr 2004 v0.36 F72603R 8.6 chip id high byte, default 0x03h, read only ? index 5ah 8.7 chip id low byte, default 0x02h, read only ? index 5bh 8.8 version id, default 0x 12 h, read only ? index 5ch 8.9 vendor id, default 0x19h, read only ? index 5dh 8.10 vendor id, default 0x34h, read onl y ? index 5eh 8.11 vender id, default 0xa0h, read onl y ? index 6ah(for aopen use only) 8.12 vender id, default 0xa0h, read onl y ? index 6bh(for aopen use only) 8.13 register f0 (test mode, default 0x00h) bit name pwd description 7 i2c_test 0 set to 1 for i2c test, disable i2c 200ns filter 6 dis_i2ctmout 0 set to 1 for disable i2ctimout 5 test_clk 0 set to 1 for test internal clock 200k, it will generate a reset for internal counters which clocked by internal clock 200k 4 en_clkin 0 enable the test clock in 3 en_clkout 0 enable the clkout output to pin 2 clkout_sel[2] 0 1 clkout_sel[1] 0 0 clkout_sel[0] 0 the clkout selection table 000 200k 001 clk_1k 010 clk_1hz 011 0.5hz 100 0.25hz 101 200k/256(tclk_out) 110 1 111 0
finte k feature integration technology inc. -13 - apr 2004 v0.36 F72603R 8.14 register f1 (test mode, default 0x00h) bit name pwd description 7 count ok 0 read only, to read test clock which is internal 200k clock divided by 256 6 speed_up 0 when set to 1, and en_clkin = 1, it will speed up the clk_2khz and clk_20hz to t_clk 5 reserved 0 reserved 4 reserved 0 reserved 3 reserved 0 reserved 2 reserved 0 reserved 1 reserved 0 reserved 0 reserved 0 reserved 8.15 regter ff (i2c addr program defaultt 0x5eh) if write 8?hc9 to register fe, that will enable i2c addr to be programmable bit name pwd description 7 i2c_addr[7] 0 i2c_addr[7] 6 i2c_addr[6] 1 i2c_addr[6] 5 i2c_addr[5] 0 i2c_addr[5] 4 i2c_addr[4] 1 i2c_addr[4] 3 i2c_addr[3] 1 i2c_addr[3] 2 i2c_addr[2] 1 i2c_addr[2] 1 i2c_addr[1] 1 i2c_addr[1] 0 i2c_addr[0] 0 i2c_addr[0]
finte k feature integration technology inc. -14 - apr 2004 v0.36 F72603R 9. electrical characteristic 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 7.0 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device 9.2 dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) parameter sym. min. typ. max. unit conditions i/o 12t - ttl level bi-directional pin with source-sink capability of 12 ma input low voltage vil 0.8 v input high voltage vih 2.0 v output low current iol 10 12 ma vol = 0.4v output high current ioh -12 -10 ma voh = 2.4v input high leakage ilih +10 a vin = vdd input low leakage ilil -10 a vin = 0v i/o 12ts - ttl level bi-directional pin with source-s ink capability of 12 ma and schmitt-trigger level input input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 3.3 v input high threshold voltage vt + 1.6 2.0 2.4 v vdd = 3.3 v output low current iol 10 12 ma vol = 0.4 v output high current ioh -12 -10 ma voh = 2.4v input high leakage ilih +10 a vin = vdd input low leakage ilil -10 a vin = 0v
finte k feature integration technology inc. -15 - apr 2004 v0.36 F72603R 9.2 dc characteristics, continued parameter sym. min. typ. max. unit conditions out 12t - ttl level output pin with source-sink capability of 12 ma output low current iol 12 16 ma vol = 0.4v output high current ioh -14 -12 ma voh = 2.4v od 8 - open-drain output pin with sink capability of 8 ma output low current iol 6 8 ma vol = 0.4v od 16 - open-drain output pin with sink capability of 16 ma output low current iol 12 16 ma vol = 0.4v i/ood 16ts - ttl level bi-directional pin, can select to od or out by register, with 16 ma source-sink capability input low threshold voltage vt- 0.5 0.8 1.1 v vdd = 3.3 v input high threshold voltage vt + 1.6 2.0 2.4 v vdd = 3.3 v output low current iol 6 8 ma vol = 0.4 v output high current ioh -16 -12 ma voh = 2.4v input high leakage ilih +10 a vin = vdd input low leakage ilil -10 a vin = 0v in t - ttl level input pin input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +10 a vin = vdd input low leakage ilil -10 a vin = 0 v in ts - ttl level schmitt-triggered input pin input low threshold voltage vt - 0.5 0.8 1.1 v vdd = 3.3v input high threshold voltage vt + 1.6 2.0 2.4 v vdd = 3.3v input high leakage ilih +10 a vin = vdd input low leakage ilil -10 a vin = 0 v
finte k feature integration technology inc. -16 - apr 2004 v0.36 F72603R 9.3 ac characteristics valid data scl sda in sda out t hd;sda t scl t hd;dat t su;sto t su;dat serial bus timing diagram t r t r serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup-up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
finte k feature integration technology inc. -17 - apr 2004 v0.36 F72603R 10. package specification 28-pin ssop(150mil) please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r. feature integration technology inc. headquarters 7f, no 31, shintai rd., jubei city, hsinchu 302, taiwan, r.o.c. tel : 886-3-6562727 fax : 886-3-6560537 www: http://www.fintek.com.tw symbol dimension in mm dimension in inch min nom max min nom max a 1.35 1.63 1.75 0.053 0.064 0.069 a1 0.10 0.15 0.25 0.004 0.006 0.010 a2 0.50 0.059 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 e 0.635 basic 0.025basic d 9.80 9.91 10.01 0.386 0.390 0.394 e 5.79 5.99 6.20 0.228 0.236 0.244 e1 3.81 3.91 3.99 0.150 0.154 0.157 l 0.41 0.635 1.27 0.016 0.025 0.050 h 0.25 0.50 0.010 0.020 zd 0.838 ref 0.033 ref 0 0 8 0 0 0 8 0
finte k feature integration technology inc. -1 - apr 2004 v0.36 F72603R 11 application circuit r6 10k r5 10k r3 4.7k u1 F72603R vsb 1 slotrst# 2 devicerst# 3 hddrst# 4 pcirstin# 5 pwokin1 6 pwokin2 7 pwokout 8 sda 9 scl 10 gnd 11 sled 12 pled 13 ps_on# 14 s5in# 15 rsmrst# 16 ss 17 lr_sen 18 gnd 19 lr_drv 20 strgate 21 usbgate 22 vccgate 23 dualgate 24 cp 25 c2 26 c1 27 vref 28 tit le size document number rev date: sheet of F72603R 0.2 fintek a 11 thursday , may 29, 2003 r8 1k r7 1k c7 1uf c6 0.1uf d4 1n4148 d3 1n5819 d2 led d1 led vsb5v vsb5v vcc12v vsb3v vsb3v s5# rsmrst# ps_on# r1 10k vram_dual hwrstin scl pcirstin# atx_pwgd q3 mosfet n pwok sda vram devicerst# hddrst# c12 1000uf slotrst# vcc3v r12 r r11 r vsb5v r2 10k jp1 1 1 2 2 3 3 vcc5v vref1.25v c13 1000uf c14 100uf dual5v q5 mosf et n q8 mosfet n q7 mosfet n vcc vsb5v vcc vsb5v q9 mosf et n usb5v vsb9v c1 1uf strgat c8 1uf c9 1uf

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